Quiz submission record for quiz4-2-1 at Tue Jul 13 20:33:58 2004:

Your Answer for Question 1:
I'm not sure I understand the question...but anyway

In C, it is:
 fun(arg 1, arg 2, ......) 
/* with argi are just the name of arguments without specifying the data type in the function call */

In Verilog, it is:
 module name(port1, port2, ......)
// "module" is the user-defined name for that module

Your Answer for Question 2:
module CLK(IN, OUT);
   input IN;
   output OUT;
   wire state0, state1, currentState;

   if(IN) #1 OUT = 1; else #1 OUT = 0

endmodule //I don't know how to write Verilog for this
          //It's wrong.
   

Your Answer for Question 3:
Wire: notC, notB, andAB, andNotC, andAC, andNotB, orResult (I think the names I chose somehow explained my answer already)

Your Answer for Question 4:
In the first "initial", there is no "#n"s (simuated time).  Because everything in Verilog happens at a particular time (or simulated time).  Without specifying the advanced time of each simulation, all the statements in this section will be executed at the same time, causing undefined results.

Time does not move along until we do something to advance it.  And without advancing time, no useful simulation can happen.


Your unique submission ID is quiz4-2-1-cs61c-cb-1089776038-1994.