Quiz submission record for quiz4-2-1 at Wed Jul 14 08:21:46 2004:

Your Answer for Question 1:
In C we pass variables by value or by address to a function without the knowledge of who is being called or what called it except that it has received values and at the end of the function, the answer will be returned to the function that called it. 
In Verilog, we normally create instantiations of the function being called and follow with a list of connections between our local signals and the ports of the function being called.

Your Answer for Question 2:
reg CLK;
repeat()
begin
#0 CLK = 0;
#4 CLK = 1;
end


Your Answer for Question 3:
not 
(w0, C),
(w1, B);

and
(w2, w0, a),
(w4, w2, b),
(w3, w1, a),
(w5, w3, c);

or
(out, w4, w5);
Therefore, 6 wires


Your Answer for Question 4:
 // #10 omitted!!
At the same time that a, b and expected get assigned their values, due to the omission of the delay, the next Verilog instruction that changes their value again would kick in too. Monitor outputs results everytime the values of any of the variables changes. In this case, the values would change all the time (without even a delay!!) and that could cause the program to crash. 


Your unique submission ID is quiz4-2-1-cs61c-cf-1089818506-1048.