Quiz submission record for quiz4-2-1 at Wed Jul 14 00:10:45 2004:

Your Answer for Question 1:
in C, the caller passes the variable or the address by specifying like

callee(arg1, arg2)

IN Verilog, we put like callee(.select(a), .in(b))
we have a dot sign in front and we matches the name in the function definition to the caller funtion by using the parenthesis

Your Answer for Question 2:
reg CLK;
initial 
begin
CLK = 1'b0;
forever
#5 CLK = ~CLK
end

Your Answer for Question 3:
There will be 4 wires needed. 2 for the output at the not gate that is used to invert B and C. Another two is for the output at the AND gates, which are 2 of them 

Your Answer for Question 4:
select=0 in0=x in1=x out=x expected=x time=0

it is because the time is not incremented manually, a, b and expected value will be fluctuating between 1 and 0. hence when the time frame is at 0, there will be undefined value. Another variable f is not defined above, hence it is an undefine value x.


Your unique submission ID is quiz4-2-1-cs61c-cg-1089789045-1975.