Quiz submission record for quiz4-2-1 at Tue Jul 13 22:27:02 2004:

Your Answer for Question 1:
The C programmer associates the order of the arguments to be what the callee's prototype is.  For example, if foo were defined as: void foo(int x, char y), then a call to foo(a,b) would only work if a were an int and b is a char.  But in Verilog, the syntax for arguments is .arg(value).  So with this, the order of arguments passed into a structure doesn't matter as long as the arguments get their correct values.

Your Answer for Question 2:
reg CLK;
initial
   begin
   CLK=1’b0;
   forever
     #2 CLK = ˜CLK;
end

Your Answer for Question 3:
E = AB*not(C) + AC*not(B) can be rewritten as:

E = A*(B*not(C)) +  A*(C*not(B))

Every inverted signal and internal wire needs to be implemented.  There are two NOT's and two ANDs hooked upto ANDs (which both require 1 wire), and the two inputs to the final OR requires 2 wires.  So the total number of wires needed is 6.


Your Answer for Question 4:
Since there is no delay, $monitor may have trouble printing correct results.  $monitor prints when one of its signals changes values, but in the second statement, 3 inputs change values without delay.  $monitor may still print the "previous" values since they are so close together.  Another reason would be that this code does not work in real life without delay implemented.


Your unique submission ID is quiz4-2-1-cs61c-cj-1089782822-149.