Quiz submission record for quiz4-2-1 at Tue Jul 13 20:56:27 2004:

Your Answer for Question 1:
Arguments to functions are associated by the order of arguments in the function definition. For example, if we have a function called foo that takes two integers x and y,
int foo (int x, int y) { ... }
then a call to foo just as foo(1,2); behinds 1 to x and 2 to y.  In Verilog, however, the caller can decide which value goes to which parameter regardless of the order in the parameter list, by specifying the parameter's name in the function call, preceded by a dot.

Your Answer for Question 2:
System clock that oscillates between 0 and 1 every 2 ns (4 ns oscillation period):

reg CLK
initial
  begin
    CLK = 1'b0;
    forever
      #2 CLK = ~CLK;
  end

Your Answer for Question 3:
We have 2 AND gates, 1 OR gate and two inverters.  Wires hold values that are in between circuit elements, so we need 2 wires for the two inverters to pass into the ANDs, and 2 more wires from the ANDs to the OR, for a total for 4 wires.

Your Answer for Question 4:
We can't really tell what $monitor will print to the screen because $monitor is supposed to print something whenever one of its signals changes.  However, in the first initial statement, there is _no_delay_ between the assignments, so a, b, and expected change "simultaneously";  $monitor should print whenever one of its signals changes, so it's undefined what it should print when 3 of its signals change.


Your unique submission ID is quiz4-2-1-cs61c-ck-1089777387-2732.