Quiz submission record for quiz4-2-1 at Wed Jul 14 03:22:04 2004:

Your Answer for Question 1:
The C programmer places them in the order that the function definintion specifies. In Verilog, although it can be done this way, they can also be bound by using the '.' convention.

Your Answer for Question 2:
reg CLK;

initial
    begin
        CLK =1'b0
        forever
              #2 CLK = ~CLK;
    end

Your Answer for Question 3:
Six would be necessary. One attached to the output of each of the two NOT, and one after each of each of the four AND's.

Your Answer for Question 4:
Each of the initialization instructions is evaluated without any delay between them, the first one will likely have no effect. The circut probably would show (in the monitor) as having taken the values of the second line. 


Your unique submission ID is quiz4-2-1-cs61c-cm-1089800524-2302.