Quiz submission record for quiz4-2-1 at Wed Jul 14 10:51:25 2004:

Your Answer for Question 1:
In C, the programmer write the function prototype of calee with argument names in the caller. In Verilog, programmers have to use .funtin(arguments) in caller.

Your Answer for Question 2:
module CLK;
reg t0;
reg a0
initial
begin
t0=1’b0;
a0 = 0
forever
#2 t0 = ˜t0;
a0 = 1
end
endmodule 


Your Answer for Question 3:
E = AB not(C) + A C not(B)
E = A(B not(C) + C not(B))
should be 10 wires


Your Answer for Question 4:
I think the programmer doesn't define the s for select or doesn't define $time. and in begin, he doesn't write the time period.


Your unique submission ID is quiz4-2-1-cs61c-cq-1089827485-2235.