Quiz submission record for quiz4-2-1 at Wed Jul 14 10:13:29 2004:

Your Answer for Question 1:
In C, the arguments are passed in the order the things are put.

In Verilog, the programmer need to physically label
which one goes where.

Your Answer for Question 2:
reg CLK;

initial
begin

CLK=1'b0;
forever
 #2 CLK = ~CLK;
end // CLK

Your Answer for Question 3:
5
If I simplify the expression
E = A.(BC- + CB-)
There will be two wires necessary to invert C and B.
There will be 1 wire to give AND of B and C-, 1 wire to
give AND of B- and C, and the last to feed the OR of
BC- and CB-.  

Your Answer for Question 4:
All the instructions will occur at the same time,
because in VERILOG, you have no clue when things will happen (So omitting # is very dangerous)



Your unique submission ID is quiz4-2-1-cs61c-eb-1089825209-352.