Quiz submission record for quiz4-2-1 at Wed Jul 14 00:27:30 2004:

Your Answer for Question 1:
The C programmer associates elements of a function at the caller with the callee by putting the variables in the function call in the same order that they appear in the argument list passed to the callee.

In Verilog, variables are associated by explicitly writing the callee arguments in parantheses with the corresponding name of the caller argument to the left of these paraentheses.  Thus, the arguments are associated by pairing them up through syntax, rather than through the order in which they are listed.

Your Answer for Question 2:
module clock;
reg clk;

initial
  begin
    #0 clk = 0;
    repeat(100)
    begin
      #2 
        if (c) c=0; else c=1;
    end
  #2 finish;
  end
endmodule



Your Answer for Question 3:
6 wires.
To and each product on both sides of the or, you need two connections.  One connection links the AB and to the first input of the second and. The second connection links up the NOT to the second input of the second and.  To or these to products together you need to more connections to take the result of each product and link it up with an or.  Thus, you 2 for each product giving you a total of 4 connections, plus 2 for the or which gives you 6 connections.

Your Answer for Question 4:
Because you have no "#n"s preceding each assignment, both assignments in the block will be executed simultaneously.
Because the code executes the code simultaneously, it may choose any combination of the variables.  
The code might want to assign s=0 and then do a=1 and b=0 from the second line to give you something you don't expect. Or the code might mean s=0; a=1; and b=1; which has has no expected value assigned to it.


Your unique submission ID is quiz4-2-1-cs61c-ee-1089790050-2524.