Quiz submission record for quiz4-2-1 at Tue Jul 13 22:38:07 2004:

Your Answer for Question 1:
In C, the programmer passes arguments to functions by filling out the function parameters with the specified variable type that matches the defined function. In Verilog, to instantiate a module and pass in local signals, the programmer must list each port in the module with each one preceded by a “.”and followed by the name of a local signal in parentheses. 

Your Answer for Question 2:
initial
begin
	CLK = 1’b0;
	forever
	#2 CLK = ~CLK;
end



Your Answer for Question 3:
If we were to setup the unsimplified version of this expression, then four wires are required:
A and B produces w0 
A and C produces w1
w0 and not C produces w2
w1 and not B produces w3
w2 or w3 produces E


Your Answer for Question 4:
The main reason for why this code would cause undefined results is due to the delays assigned at the logic gates. If there were added delays to the circuit elements, then the initial output at time = 0 is undefined because it takes a certain delay before the output takes on the new value. 

In addition, because the 10 ns delay is omitted, at time = 0 when the lines are executed, the selector would not be able to differentiate as to pick the value of a= 0 or a = 1 since they occur simultaneously. Hence, the output is undefined.  



Your unique submission ID is quiz4-2-1-cs61c-ei-1089783487-2976.