Quiz submission record for quiz4-2-1 at Tue Jul 13 20:35:17 2004:

Your Answer for Question 1:
Type the name, then "(", then arguments separated by commas, then ")".  Verilog is the same.

Your Answer for Question 2:
initial
  begin
     CLK=1'b0;
     forever
       #4 CLK = ~CLK
  end

Your Answer for Question 3:
       _    _
E = A(BC + CB)

      _
3 for BC
      _
3 for CB

2 more for input to final AND

1 more for output

Total: 9

Your Answer for Question 4:
The undefined result could be the same as if s=0, a=1, b=0, expected=1.  I think a second declaration would overwrite the first.  Why?  I don't know. If it's undefined, anything can happen. 


Your unique submission ID is quiz4-2-1-cs61c-ej-1089776117-1284.