Quiz submission record for quiz4-2-1 at Tue Jul 13 23:16:24 2004:

Your Answer for Question 1:
Formatwise, it is very similar.  The C programmer just has the arguments in the function call in the same order that they appear in the function definition foo(x, y, z).  Verilog is very similar in that it looks the same, except that arguments to a module in Verilog do not have to be in the same order if their identity is specified; otherwise, it is much the same.  Like module(.in(x), .out(y))

Your Answer for Question 2:
reg CLK

initial
  begin
    CLK = 1'b0
    forever
    #2 CLK = ~CLK

Your Answer for Question 3:
There will need to be six wires.  For the first product in the expression, the inputs A and B can be sent directly to an AND gate, and its output gets sent to a wire.  C will need to be sent to a NOT, and its output sent to a wire.  These two wires will be sent to an AND gate to get the value of the first sum.  For the second part, A and C are sent to an AND gate, whose output is sent to a wire.  B inverted is sent to a whle, and AC and !B are sent to an AND gate whose output is a wire.  The wires carrying the values of AB!C and AC!B are then sent to an OR gate, whose value is sent directly to E.

Your Answer for Question 4:
The problems would appear if there is delay in the module that s, a, and b are ports of.  If that module has a delay, say of 5 ns, then before it can finish calculating what its output should be for the first set, new input is given to it.  Since the input is changed in the middle of the process, and since a and b are flipped, it seems likely that the process will head down an opposite branch than it was first intended.  SInce $monitor displays any changes, it will show some undefined output because what was supposed to be the output of the first set of arguments has not yet been totally defined when it is changed.


Your unique submission ID is quiz4-2-1-cs61c-el-1089785784-475.