Quiz submission record for quiz4-2-1 at Tue Jul 13 19:39:26 2004:

Your Answer for Question 1:
In C, the caller must specify the arguments in the correct order. But in Verilog, if we use the dot operator, we can put the arguments in the function call in different order

Your Answer for Question 2:
initial
  begin
  CLK=1’b0;
  forever
  #2 CLK = ˜CLK;
end

Your Answer for Question 3:
E = A(B(~c)+c(~B))
There are 3 AND gates and one OR gate
THere are 8 wires
The ouput of (B(~c)+c(~B)) is connected an AND gate with A

Your Answer for Question 4:
Since the code doesn't specify the time,  the two assignment to a and b occurs at the same time. So Verilog will not know what the values of a and b are, so an undefined result will be produced


Your unique submission ID is quiz4-2-1-cs61c-en-1089772766-1954.