Quiz submission record for quiz4-2-1 at Wed Jul 14 01:30:13 2004:

Your Answer for Question 1:
It calls the function with the arguments like func(arg1, arg2, arg3). In Verilog, one would list the input ports preceded by a '.' and followed by the local signal name in parentheses. 

Your Answer for Question 2:
initial
  begin
     CLK=1'b0;
     forever
     #2 CLK = ~CLK;
  end

Your Answer for Question 3:
We need three wires, one each for A, B, and C. We can get Bbar and Cbar from using not on B and C respectively, and E is going to be the output port. 

Your Answer for Question 4:
The undefined results would be that both of the instructions would happen at the same, so we might get 0 or 1. This would happen because the two instructions are executed simultaneously so we don't know what values a and b actually end up having. 


Your unique submission ID is quiz4-2-1-cs61c-ep-1089793813-2748.