Quiz submission record for quiz4-2-1 at Wed Jul 14 02:06:56 2004:

Your Answer for Question 1:
C programmers pass arguments as parameters to a function to associate the arguments between caller and callee. But after the data is sent to the callee, it is temporarily out of the caller's hands. In Verilog, there are no functions so to speak, but modules do take arguments like normal functions, except they are manipulated by the caller outside of the called module.

Your Answer for Question 2:
reg CLCK;
initial
  begin
    CLCK = 1'b0;
    forever
      #2 CLCK = ~CLCK;
  end

Your Answer for Question 3:
6 wires will be needed. AB will run directly into an AND gate which will output into one wire. Then C will run to a NOT gate which will output into a second wire. These two wires will input into a second AND gate which outputs into a third wire. A similar layout expresses the second term for three more wires. Two of the six wires run into the OR gate which outputs E. The inputs and output do not require separate wires, so six will suffice.

Your Answer for Question 4:
The assignments after 'begin' happen at the same time; 'a' and 'expected' are both simultaneously assigned different values, which will cause undefined results since it is not clear which values those variables are supposed to take on. Thus Verilog will print them as undefined.


Your unique submission ID is quiz4-2-1-cs61c-eq-1089796016-1707.