Quiz submission record for quiz4-2-1 at Tue Jul 13 19:36:30 2004:

Your Answer for Question 1:
THe C programmer assciates the arguements of a function at the caller with the callee by using the function name and the arguements in parenthesis. Verilog does this by having a user-defined module, followed by a list of signals. These signals define the interface of the module to other modules. When a module is instaintianted, these port like things are bound together to other signals for interconnection with other modules.

Your Answer for Question 2:
module CLK()
input D;
input CLK, RST;
output Q;
reg Q;
always @ (posedge CLK)
if (RST) #1 Q = 0; else #1 Q = D;
endmodule 

module parityChecker (OUT, IN, CLK, RST);
output OUT;
input IN;
input CLK, RST;
wire currentState, nextState;
#1 xor (nextState, IN, currentState);
buf (OUT, nextState);
endmodule 

Your Answer for Question 3:
5 wires will be needed.

Your Answer for Question 4:
undefined result might mean that it produces something other than a 0 or a 1. Add this might be because the signals are getting crossed.


Your unique submission ID is quiz4-2-1-cs61c-et-1089772590-1923.