Quiz submission record for quiz4-2-1 at Tue Jul 13 20:25:15 2004:

Your Answer for Question 1:
In C, you would have to match up the arguments in order. So, when you call a function, the arguments you pass in must match up with the arguments in the function, otherwise you'll get wrong type of variable (a type mismatch) or just pass in the wrong variable to be used in the function.

In Verilog, you can make connections between local signals and module ports by listing the ports of the function is arbitrary order, each order preceded by a "." and followed by the name of a local signal in parentheses. The main benefit of this form is that order does not matter which makes changes easier later on.

Your Answer for Question 2:
....

reg CLK;

initial
begin
CLK=1'b0;
forever
#2 CLK = ~CLK;
end

...

Your Answer for Question 3:
You will need six wires.

1) To hold the result of A AND B so we can compare with NOT C.
2) To hold the result of NOT C to compare against the result from wire 1.
3) To hold the result of A AND C so we can compare with NOT B.
4) To hold the result of NOT B to compare against the result from wire 3.
5) To hold the result of comparing wire 1 AND wire 2.
6) To hold the result of comparing wire 3 AND wire 4.

5 and 6 are needed for the OR which afterwards will pass to the output.

Your Answer for Question 4:
Since the #'s are missing from the beginning, all the statements in the first part will occur at the same time (the start of the simulation), which will cause undefined results. In Verilog, you actually have to advance the clock yourself (otherwise you get an unrealistic simulation) with the #(number) at the beginning of a line.


Your unique submission ID is quiz4-2-1-cs61c-ev-1089775515-2269.