Quiz submission record for quiz4-2-1 at Tue Jul 13 23:19:40 2004:

Your Answer for Question 1:
In C, the association of the arguments at the caller with the callee is determined by the order. For example, if a function is defined "int func(int x, int y)" and invoked "func(hi, bye)", then "hi" is associated with "x" and "bye" with "y".

This is also allowed in Verilog, but you can also use the "dot notation", where the caller has to follow up with the parameter name as specified in the module and the name of the local variable in parenthesis. Order does not matter, so in the example above, the following would be acceptable: "func(.y(hi), .x(bye)".

Your Answer for Question 2:
module CLK;
  reg tick;
  initial
    begin
      tick = 1'b0
      forever
        #2 tick = ~tick;
    end
endmodule


Your Answer for Question 3:
Total of six wires would be necessary for this module. First, looking at AB!C, since the logic gates only has two inputs, must be a combination of three logic gates: (1) AND A and B, (2) NOT C, (3) AND results from 1 and 2. So this requires two intermediary wires. The same applies to AC!B. Lastly, to combine these two terms together by taking the results from both sets of logic gates, we need two more wires. In total, we need six.

Your Answer for Question 4:
Undefined result in Verilog is indicated with the symbol "x". The output of this code is undefined because the lines "s=0; a=0; b=1; expected=0;" and "a=1; b=0; expected=1;" would be run simultaneously. Since a and b cannot be both 0 and 1 at the same time, these variables are undefined.


Your unique submission ID is quiz4-2-1-cs61c-ew-1089785980-2397.