Quiz submission record for quiz4-2-1 at Wed Jul 14 07:23:43 2004:

Your Answer for Question 1:
If I understand the question,using prototype of a callee, the caller know how to use callee as arguments.
In verilog however there is no assignment statement.we use
modules to build heirarchy but no real action will take place.

Your Answer for Question 2:
initial
begin
clk= 1'b0;
forever
#2 clk = -clk;
end

Your Answer for Question 3:
we need six wires:
notc,notb,ab,ac,abnotc,acnotb;

Your Answer for Question 4:
In verilog time doesn't move a long untill we do something to advance it.The omition of #10, would cause the statements to occur at the same time(the start of simiulation)causing undefined results.So no useful simulation can happen.


Your unique submission ID is quiz4-2-1-cs61c-fx-1089815023-214.