Answer from cs61c-ei (Jing Chen 16669246) for Question 2
The RegWrite signal essentially controls whether or not a register is writing data to a register (as opposed to reading data). Writes are all controlled by this signal, which must be asserted for a write to occur at clock edge. Because writes are edge-triggered, all write inputs (data to be written, register number, and write control signal) must all valid at clock edge. This design will allow the register to read and write the same register within a clock cycle.