Answer from cs61c-ed (Cory Benavides 14101530) for Question 3
The extra add unit provides the memory address to jump to if the branch logic is satisfied.  The ALU outputs a value that tells the subsequent logic if it should take the branch address or not.  Both values are needed.  Now if (and I don't know how the rest of the system works) the instruction remains at the input over several clock cycles, then it is concievably possible to use only the ALU.  The branch logic output would be output on one clock cycle and on another, the branch target address would be output.  This would slow down the system, so it wouldn't be advisable.