Quiz submission record for quiz5-1-1 at Mon Jul 19 09:16:45 2004:

Your Answer for Question 1:
making the common case fast and implementing the instruction set with regularity and simplicity in mind will yield us better clock rate and CPI.  Also the simplicity and regularity of the instruction set simplifies the implementation  by making the execution of many of the instruction classes similar

Your Answer for Question 2:
It occurs at the clock edge and stores(writes) the processor's 32 registers in a register file.   

Your Answer for Question 3:
The add unit computes the branch target as the sum of the incremented PC and the sign-extended, lower 16 bits of the instruction shifted left 2 bits.  A single ALU cann't do both jobs because branches are delayed in a MIPS instruction set, which must be accounted for by adding an adder.


Your unique submission ID is quiz5-1-1-cs61c-cl-1090253805-2498.