Quiz submission record for quiz5-1-1 at Mon Jul 19 10:07:18 2004:

Your Answer for Question 1:
From a hardware perspective, 
by having regularity, all logic elements can have
similar structures, so it is much easier to make everything look like each other.
By having simplicity, it is easy, because the 
number of elements in the hardware can be much smaller
while having the same capacity.

Your Answer for Question 2:
It is a control signal that will tell
the state element to not update specifically,
in a clock-edge, if the element isn't updated every
clock-edge.
It's a control signal that needs to be 
asserted to make a write at the clock edge.

Your Answer for Question 3:
The purpose of the add-unit
because it is for the jal or jump operation.

It would be possible to do so by placing 
mux before the ALU, which will choose between
the sign-extended and the readdata2 from the ALU




Your unique submission ID is quiz5-1-1-cs61c-eb-1090256838-2154.