Quiz submission record for quiz5-1-1 at Sun Jul 18 22:09:49 2004:

Your Answer for Question 1:
From the hardware perspectives, designers follow principles such as “making the common case fast” and keeping the instruction set both regular and simple. First off, any sort of added logic or area = cost, and designers want chips to have the most functionality at the lowest cost. In addition, they want to keep everything consist to cater towards backwards compatibility later on. 

Your Answer for Question 2:
The RegWrite signal essentially controls whether or not a register is writing data to a register (as opposed to reading data). Writes are all controlled by this signal, which must be asserted for a write to occur at clock edge. Because writes are edge-triggered, all write inputs (data to be written, register number, and write control signal) must all valid at clock edge. This design will allow the register to read and write the same register within a clock cycle. 

Your Answer for Question 3:
The separate Add unit is used for branch instructions and computes branch target as the sum of the increment PC and the sign-indexed, lower 16 bits of the instruction shifted left 2 bits. It would not be possible for a single ALU to do the functions of the ALU and the Adder.  The reason for this is that all branch datapaths must do two operations of 1) computing the branch target address (done with Adder) and 2) comparing register contents. (done with ALU) . Because adders are logic units that have no state, there will be no way for a single ALU to handle two operations and remember the value calculates in the first one. 


Your unique submission ID is quiz5-1-1-cs61c-ei-1090213789-2778.