Answer from cs61c-cj (Peter Lau 16539384) for Question 1
A branch delay slot is the instruction following a branch instruction.  The MIPS assembler will automatically arrange instructions to get this branch delay behavior without intervention by the programmer.  It fills this branch delay slot with an instruction that is not affected by the branch so it doesn't "waste" CPU cycles for the pipelined CPU while it determines whether or not to take the branch.