Answer from cs61c-ck (Allen Lee 16583554) for Question 1
In pipelining, a branch delay slot is a slot for an instruction that comes right after a branch instruction.  Since branches stall the pipeline by one cycle due to having to check whether not or the branch is taken, we have a bubble, which is wasted time in which we can execute an instruction.  The MIPS compiler will put an instruction in this branch delay slot that is not affected by the branch.