Answer from cs61c-ec (Osbert Orr 16671538) for Question 1
The branch delay slot is a side-effect of pipelined architectures due to the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter. Each cycle where a stall is inserted is considered one branch delay slot.