Answer from cs61c-aj (Kevin Li 15855812) for Question 2
This is a data hazard. Because the line following the load word instruction add $t1 $t0 $t0 needs register $t0 to have its value. But through pipelining, $t0 is not fully loaded because the load word instruction is not fully finished when add instruction is executed. We can use forwarding which means that before register $t0 is even written the value is passed onto the add so that both write and adding can be executed at one clock cycle. A software scheme that can reduce this is to change the instructions around so that no instruction will depend on the instruction immediately preceeding it.