Answer from cs61c-cd (Charles Leung 15905350) for Question 2
the lw command takes more time than a and command.  In fact, it take 2 ns longer because it has to have a data access process.  Therefore,  the add would have to wait a little bit of time and out pipeline (the graphical picture) would have an idle hole in it.  Since, these two  operations depend on one another, we need to  wait for lw to complete before add does.  We could reduce the penalty by simply makeing wires shorter (althoguh that would speed everything up...).