Answer from cs61c-cj (Peter Lau 16539384) for Question 2
This sequence of instructions cannot run at full speed on the pipelined datapath without special hardware because at exactly one pipeline stage after the load word, $t0 does not have its updated value before add tries to use it.  To reduce the performance penalty, the MIPS processor can stall for one instruction until the next one is executed to give the load word instruction enough time to store its value into $t0.  The processor will also need to use forwarding to get the "value" of $t0 before it gets stored into the registers.  This will require additional forwarding hardware.