Answer from cs61c-ew (Joo-Rak Son 16103505) for Question 2
These instructions cannot be pipelined straightforwardly because the second instruction uses t0 which is determined in the first instruction. To reduce this penalty,
(1) Implement new wire so that the memory fetched from lw instruction can go directly into ALU unit so that the second instruction can be executed ASAP.
(2) Come up with a software solution which inserts an unrelated instruction inbetween this bubble, similar to what we do with brach delay slots.