Answer from cs61c-aj (Kevin Li 15855812) for Question 3
It would break down because when a previous instruction is writing to the data memory or accessing it, another instruction in the pipeline will want to access it too to get the next instruction; however, it is being used by a previous instruction in the pipeline which will cause it to stall. This is why we need to have two different memory module in order to access the instruction memory and write or access data from data memory at the same time.