Answer from cs61c-cj (Peter Lau 16539384) for Question 3
This will break our pipelining scheme because there are two stages in the pipelining scheme that require memory accesses: instruction fetch and memory accesses.  If these were using the same memory module, the processor cannot start an instruction whose instruction fetch or memory access conflicts with a running instruction's use of the memory module.  For the pipeline scheme to run at full speed, each of the 5 stages of pipelining must have its own individual hardware.