Answer from cs61c-ei (Jing Chen 16669246) for Question 3
This would break our pipelining scheme because we would be traveling backwards when trying to access data memory since that occurs at a later stage in the pipeline. This would make reading files from registers and retrieving data from memory extremely complicated since we would need to separate stages out so that these processes are happening independently (so we are not washing the same load twice, missing loads, etc.)