Answer from cs61c-ej (Leon Wang 16247444) for Question 3
Assuming that the order is Instruction fetch, Reg, ALU, Data access, Reg, if we have more than three instructions being executed per clock cycle, Instruction fetch and Data access will be run at the same time.  Therefore if there were only 1 memory module, it wouldn't work because that memory module would be used by instruction fetch and data access in the same clock cycle and that's not really possible.