Answer from cs61c-ew (Joo-Rak Son 16103505) for Question 3
Having only one memory module means that each instruction has to spend two stages at this memory module (IF and WB). Normally, each instruction has to spend only one stage at each memory module.
This means that in our pipelining scheme, the next instruction in line has to wait for two stages instead of one, so it will half the speed of our processor.