Quiz submission record for quiz5-2-2 at Thu Jul 22 10:12:31 2004:

Your Answer for Question 1:
A branch delay slot is created when we wait for the result of a branch when pipelining. It can usually be filled with useful instruction.

Your Answer for Question 2:
The second instruction requires the value in $t0, which is still in the pipeline when the second instruction started.

We can use forwarding or bypassing to get the result from the first instruction early.

Your Answer for Question 3:
Yes. Our pipelining scheme requires two memories because it read AND write data in each cycle . With only one memory module, it would not work.


Your unique submission ID is quiz5-2-2-cs61c-ac-1090516351-708.