Quiz submission record for quiz5-2-2 at Thu Jul 22 10:13:12 2004:

Your Answer for Question 1:
The branch delay slot is basically the instruction that is right after a branch call.  In pipelining, a branch instruction cannot be decided until after the next instruction, so the delay slot is added.

Your Answer for Question 2:
This cannot run at full speed because lw does not store the new data into $t0 until stage 5 but the add instruction requires the information in stage 2.  We can use forwarding to give $t0 to add before it is actually written to memory.

Your Answer for Question 3:
This would cause a structural hazard because every fourth instruction would run into the problem of having to access the instructional memory while the first one is accessing the data memory at the same time.


Your unique submission ID is quiz5-2-2-cs61c-ae-1090516392-748.