Quiz submission record for quiz5-2-2 at Wed Jul 21 17:21:50 2004:

Your Answer for Question 1:
It is the the instruction slot immediately following the branch instruction. No matter if the branch is taken or not the branch delay slot is always executed. This is because hardware is implemented so that it will not be slowed down. In case if the branch is not taken no time is wasted on a useless stall. If it is taken then the branch delay slot instruction that is executed is tossed and ignored.

Your Answer for Question 2:
This is a data hazard. Because the line following the load word instruction add $t1 $t0 $t0 needs register $t0 to have its value. But through pipelining, $t0 is not fully loaded because the load word instruction is not fully finished when add instruction is executed. We can use forwarding which means that before register $t0 is even written the value is passed onto the add so that both write and adding can be executed at one clock cycle. A software scheme that can reduce this is to change the instructions around so that no instruction will depend on the instruction immediately preceeding it.

Your Answer for Question 3:
It would break down because when a previous instruction is writing to the data memory or accessing it, another instruction in the pipeline will want to access it too to get the next instruction; however, it is being used by a previous instruction in the pipeline which will cause it to stall. This is why we need to have two different memory module in order to access the instruction memory and write or access data from data memory at the same time.


Your unique submission ID is quiz5-2-2-cs61c-aj-1090455710-1600.