Quiz submission record for quiz5-2-2 at Wed Jul 21 23:52:12 2004:

Your Answer for Question 1:
Because branches cause pipeline problems, if there are statements preceding a branch that do not effect the branch, the branch might be executed early and the slots that are avaliable before the branch destination is known, branch delay slots, are filled with these instructions.



Your Answer for Question 2:
These instructions cannot be run at full speed because the second instruction depends on the result of the first.  The scheme that allows us to reduce the performance penalty is forwarding, or returning the results from a certain stages early.

Your Answer for Question 3:
If there were only one memory module, two instructions could be accessing it at the same time because one could be writing it's result to memory and another could be trying to fetch it's instruction.




Your unique submission ID is quiz5-2-2-cs61c-au-1090479132-1156.