Quiz submission record for quiz5-2-2 at Thu Jul 22 03:16:32 2004:

Your Answer for Question 1:
The delayed branch always executes the next sequential instruction, with the bench taking place after that one instruction delay.
it makes the pipeline proceeds at full speed.

Your Answer for Question 2:
In these two instructions, add instruction is depending on the result after executing lw instruction.
forwarding can get reduce the proformance penalty.

Your Answer for Question 3:
If we had a single memory instead of two memories. If the pipeline had a fouth instruction, we would see that in the same clock cycle that the first instruction is accessing data from memeory while the fourth instruction is fetching an instrcution from that same memory. That coulg lead a structure hazard.


Your unique submission ID is quiz5-2-2-cs61c-aw-1090491392-2886.