Quiz submission record for quiz5-2-2 at Thu Jul 22 01:30:05 2004:

Your Answer for Question 1:
A branch delay slot is the slot directly after a delayed branch instruction.  It is filled by an instruction that does not affect the branch, but is still valid and useful.

Your Answer for Question 2:
This will not work because it is data hazard; that is, the add instruction depends on the lw instruction since lw is putting a value into $t0 that add then needs.  You can use forwarding to help resolve this data hazard.

Your Answer for Question 3:
This will break our pipelining scheme because it would create a structural hazard.  For example, having only one memory could mean that in the same clock cycle that one instruction is accessing data, another instruction could be fetching an instruction from that same memory.


Your unique submission ID is quiz5-2-2-cs61c-ax-1090485005-1205.