Quiz submission record for quiz5-2-2 at Thu Jul 22 01:17:29 2004:

Your Answer for Question 1:
If next instruction of branch does not affect branch, then we move it to delay slot and excute branch, and excute delayed instuction in next cycle. 

A branch delay slot is for avoiding control hazards. 
 

Your Answer for Question 2:
Because of data hazard in $t0. We can't use $t0 before 4th stage.

It can be reduced by delayed load - it menas we should use instruction independent of load in next of lw.

Your Answer for Question 3:
Because PC and regfile can't read simultaneously from memory if we have only 1 memory module. (This is a kind of structural hazards. In figure 6.3, we can't excute 4th instruction, becuse lw needs reading from memory.)


Your unique submission ID is quiz5-2-2-cs61c-bd-1090484249-1678.