Quiz submission record for quiz5-2-2 at Wed Jul 21 23:11:57 2004:

Your Answer for Question 1:
A branch delay slot occurs because a branch always executes the next instruction irrespective of where its going to branch. This allows for faster processing since we do not have to wait to figure out the offset and if its more likely that the branch will fail, it allows us to execute the next instruction without any delay. 

Your Answer for Question 2:
The add instruction depends on the value stored in $t0. Unfortunately, since the instruction just before that is a lw we are forced to spend a cycle as a nop. However, if the hardware implements forwarding this problem can be circumvented. 

Your Answer for Question 3:
Yes, we can access one piece of hardware at a time and if the instruction and data memory were combined, this would mean that in the pipelining process, we would have to completely wait until all instruction and data accesses are completed before we start the next instruction and that would essentially break the pipeline. 


Your unique submission ID is quiz5-2-2-cs61c-cf-1090476717-1706.