Quiz submission record for quiz5-2-2 at Thu Jul 22 10:00:51 2004:

Your Answer for Question 1:
a branch delay slot is a single cycle delay that comes after a conditional branch instruction  has begun execution, but before the branch condition has been resolved, and the branch target address has been computed. It is a feature of several RISC designs, such as the SPARC.

Your Answer for Question 2:
notice that we need $t0 to get resolved in line 1 before we can execute line 2 of the code. we could remove this dependence to increase performance in code by tying code less.

Your Answer for Question 3:
because we'll need more instructions depending on each other. in other words, we'll have to execute the values in the registers before using them in other lines of code.. simplification of hardware = complexity in software which breaks pipelining


Your unique submission ID is quiz5-2-2-cs61c-ch-1090515651-2414.