Quiz submission record for quiz5-2-2 at Wed Jul 21 17:22:20 2004:

Your Answer for Question 1:
A branch delay slot is the instruction following a branch instruction.  The MIPS assembler will automatically arrange instructions to get this branch delay behavior without intervention by the programmer.  It fills this branch delay slot with an instruction that is not affected by the branch so it doesn't "waste" CPU cycles for the pipelined CPU while it determines whether or not to take the branch.

Your Answer for Question 2:
This sequence of instructions cannot run at full speed on the pipelined datapath without special hardware because at exactly one pipeline stage after the load word, $t0 does not have its updated value before add tries to use it.  To reduce the performance penalty, the MIPS processor can stall for one instruction until the next one is executed to give the load word instruction enough time to store its value into $t0.  The processor will also need to use forwarding to get the "value" of $t0 before it gets stored into the registers.  This will require additional forwarding hardware.

Your Answer for Question 3:
This will break our pipelining scheme because there are two stages in the pipelining scheme that require memory accesses: instruction fetch and memory accesses.  If these were using the same memory module, the processor cannot start an instruction whose instruction fetch or memory access conflicts with a running instruction's use of the memory module.  For the pipeline scheme to run at full speed, each of the 5 stages of pipelining must have its own individual hardware.


Your unique submission ID is quiz5-2-2-cs61c-cj-1090455740-1646.