Quiz submission record for quiz5-2-2 at Thu Jul 22 04:10:01 2004:

Your Answer for Question 1:
In pipelining, a branch delay slot is a slot for an instruction that comes right after a branch instruction.  Since branches stall the pipeline by one cycle due to having to check whether not or the branch is taken, we have a bubble, which is wasted time in which we can execute an instruction.  The MIPS compiler will put an instruction in this branch delay slot that is not affected by the branch.

Your Answer for Question 2:
That sequence of instructions causes problems because $t0 is used by add right after we load a value from memory into it - in pipelining, data isn't written back into the register until the 5th stage, but trailing instruction needs the data right before its 3rd stage.  This would mean that our program has to stall for a bit to wait for the value to be put into the reg file before using it.  We fix this by forwarding the value directly from the memory into the input to the ALU for the add instruction without passing it into the reg file.

Your Answer for Question 3:
Using one memory module for two purposes is a structural hazard.  Instruction fetching is the first stage and writing to memory is the fourth stage, so any pipeline with 4 or more stages will fail because we'd try to read and write to the same memory module on the same cycle, which could cause major problems.


Your unique submission ID is quiz5-2-2-cs61c-ck-1090494601-1746.