Quiz submission record for quiz5-2-2 at Thu Jul 22 09:46:36 2004:

Your Answer for Question 1:
a branch delay slot is where compiler and assembler try to place an instruction that is always executed after a branch.
  

Your Answer for Question 2:
in the pipeline, 0($s1) will be executed with add $t1 $t0 $t0 at the same time. In this case, $t0 is not avaliable, when we do add instruction.
we can use branch delay slot or other delay software to delay add instruction to get the value in $t0.



Your Answer for Question 3:
Pipelined control strives for 1 clock cycle per instruction. having only 1 memory module will cause that there is not enough delays for instructions. So, this will break our pipelining scheme.


Your unique submission ID is quiz5-2-2-cs61c-cq-1090514796-488.