Quiz submission record for quiz5-2-2 at Thu Jul 22 00:31:10 2004:

Your Answer for Question 1:
The branch delay slot is a side-effect of pipelined architectures due to the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter. Each cycle where a stall is inserted is considered one branch delay slot.

Your Answer for Question 2:
Before lw can load $t0 from $s1, add already tries to access $t0. A stall needs to be inputted into either the hardware of software so as to enable lw to finish looking up the address, finding the value and then inserting it into $t0 ready for use by add.

Your Answer for Question 3:
This will break our pipelining scheme because it is taking away a means to process data. It is just like the washer and dryer analogy where in this case the dryer is taken away and the washer is expected to both wash and dry.




Your unique submission ID is quiz5-2-2-cs61c-ec-1090481470-3051.