Quiz submission record for quiz5-2-2 at Thu Jul 22 10:30:33 2004:

Your Answer for Question 1:
When a branch is encountered, the next pipelined command may or may not be the intruction to be executed.  As such, the next instruction slot can be filled with an instruction that needs to be executed from another location in the program.  This is a branch delay slot.

Your Answer for Question 2:
This won't run as efficiently as possible because when pipelined, lw will write the data to the register two clock cycles after add tries to access it.  To minimize the performance penalty, forwarding hardware can be implemented that directly carries the results from lw's data access to add's ALU stage.  This will decrease the penalty to a one clock cycle loss.

Your Answer for Question 3:
This will break the pipelining scheme because two consecutive intructions will attempt to read from the memory at the same time.


Your unique submission ID is quiz5-2-2-cs61c-ed-1090517433-1517.